Coding device and communication system using the same

ABSTRACT

A coding device comprises a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block comprising a plurality of the interleaved words, and a puncturing circuit or repeating circuit for puncturing or repeating bits from the data block. The puncturing or repeating circuit uses a deleting or repeating pattern to provide data words for transmission during respective frames of a transmission channel. The deleting or repeating pattern is selected depending upon the characteristics of the coding circuit and of the interleaving circuit. The coding device is for use in a cordless communication system.

[0001] This invention relates generally to digital communicationsystems, and more particularly to a communication system using coding ofthe digital input to generate a coded input having a greater number ofbits than the digital input.

[0002] Forward Error Correction (FEC) operates in this manner, andconvolutional coding is one example of forward error correction system.

[0003] In a convolutional coding system, a digital input is coded by aconvolutional coding circuit so that for every number k of bits inputtedinto the convolutional coding circuit, a greater number n of bits isprovided as output. A coding rate for the convolutional coding circuitis defined as the ratio of the number k of input bits to the number n ofcoded output bits. Thus, for example, the coding rate is ½ when for eachbit inputted into the convolutional coding circuit, two output bitsresult. This increase in the number of bits results in a decrease in thesignal bit rate.

[0004] Various conventional convolutional coding algorithms areavailable, each with a specific coding rate. It may be desirable toadjust the coding rate so that the data rate for the output of thecircuit matches the requirements for the remainder of the communicationcircuitry including the communication channel. For example, in order toincrease the code rate it is known to pass the convolutional codedoutput through a puncturing circuit which includes a deletion patternfor removing selected bits from the convolutional coded output.Alternatively, in order to reduce the code rate it is possible to passthe output through a repetition circuit for repeating selected bits ofthe output.

[0005] U.S. Pat. No. 5,668,820 and U.S. Pat. No. 5,511,082 each disclosea digital communication system having a punctured convolutional codingsystem of the type described above.

[0006] The invention is particularly concerned with a coding devicewhich has a coded output and in which a number of words of the codedoutput signal are interleaved. Interleaving is a well known techniqueused for improving the error performance of a transmission system. Thereis an increasing requirement for flexibility in communication systems,for example the ability to handle data having different characteristics,such as bit rate, interleaving depth, variable rates of data etc. Theuse of a conventional variable rate convolutional coding circuit (orother FEC coding circuit) in a coding device having interleaving of thecoded output requires the interleaving circuitry to be adaptive to theoutput bit rate of the convolutional coder. The applicant has thereforeappreciated that the interleaving of data should be performed aftercoding, but before rate matching of the data stream (i.e. beforepuncturing or bit repetition). However, this introduces the problem thatthe puncturing or bit repetition performed by the rate matching circuitmay not be appropriate for the bit structure generated by theinterleaving circuit. For example, there is the possibility that thebits selected for puncturing bits provide information concerning thesame or adjacent bits in the digital input. This increases theprobability of error in the transmission in respect of that part of theinput signal.

[0007] According to a first aspect of the invention there is provided arate matching circuit for adjusting the number of bits in a data block,the data block comprising a plurality of interleaved words generated bythe action of an interleaving circuit on a coded output generated by theaction of a coding circuit on a digital input, the coded output having agreater number of bits than the digital input, the rate matching circuithaving means for adjusting the number of bits in the data block using arate matching pattern to provide data bits for transmission duringrespective frames of a transmission channel, characterised in that meansare provided for selecting the rate matching pattern depending on thecharacteristics of the coding circuit and of the interleaving circuit.

[0008] By repeating pattern is meant a pattern (of 1's and 0's)indicating which bits within a respective data block are to be repeated.

[0009] In accordance with the present invention, the interleavingcircuit does not need to be adaptive, because it is selected forinterface with a coding circuit having a fixed code rate or a limitednumber of rates for a variable rate data source. The puncturing circuitor repeating circuit then operates on the interleaved words in order toadjust the output bit rate to be appropriate for transmission over thetransmission channel. The deletion or repetition pattern is thenselected in such a way that (i) in the case of deletion of bits, thepuncturing has least at least detrimental effect to the digital circuit)which has been coded and interleaved before input to the puncturingcircuit or (ii) in the case of repetition of bits, the repetition hasthe most beneficial effect for the output for transmission and is notconcentrated at one portion of the digital input.

[0010] Also, according to the invention, the single puncturing orrepeating stage, which effects rate matching of the input signal, can beused to control the transmission quality of the input signal (byaltering the forward error correction characteristics) as well asmanipulating the output bit rate to be suitable for subsequenttransmission, for example to match the maximum bit rate of thetransmission channel. This avoids the need for separate rate matchingstages for quality of service requirements and for channel capacityconsideration.

[0011] The pattern for each interleaved word within the data block maybe offset with respect to the adjacent interleaved word or words withinthe block. For a block interleaving circuit, the targeting of differentbits within adjacent words of the interleaved block is one way ofpreventing adjacent bits from the coded output word from being targetedby the repetition/deletion pattern.

[0012] The pattern may be selected as a function of the interleavingdepth of the interleaving circuit.

[0013] The coding preferably comprises convolutional coding, and thedeletion or repetition pattern will take into account, for example, theconstraint length of the convolutional coding circuit.

[0014] The rate matching circuit enables the output bit rate to becontrolled, and this has particular application when a number of digitalinputs are to be multiplexed on to a single carrier. For this purpose, acommunication system may comprise a plurality of coding devices, eachfor coding a respective digital input, and a multiplexer for combiningoutput data words of the coding devices for subsequent transmission bythe transmission system on the single transmission channel. The outputsof different coding devices may be selected to have different datarates, with the combined data rate corresponding to the channel capacityof the transmission channel.

[0015] According to a second aspect of the present invention there isprovided a coding device comprising a rate matching circuit made inaccordance with the present invention, further comprising aninterleaving circuit and a coding circuit.

[0016] According to a third aspect of the present invention there isprovided a decoding device for decoding a signal coded by a codingdevice of the invention, and comprising a data reconstruction circuitfor reconstructing the interleaved words, a de-interleaving circuit anda channel decoder.

[0017] According to a fourth aspect of the present invention there isprovided a communication system comprising a transmitter having a codingdevice of the invention and a transmission system for transmitting theoutput data Words of the coding device. A receiver of the systemincludes the decoding device. According to a fifth aspect of the presentinvention there is provided a method of operating a rate matchingcircuit to adjust the number of bits in a data block, the data blockcomprising a plurality of interleaved words generated by the action ofan interleaving circuit on a coded output generated by the action of acoding circuit on a digital input, the coded output having a greaternumber of bits than the digital input, the rate matching circuitadjusting the number of bits in the data block using a rate matchingpattern to provide data bits for transmission during respective framesof a transmission channel, characterised by selecting the rate matchingpattern depending on the characteristics of the coding circuit and ofthe interleaving circuit.

[0018] This invention will now be described by way of example withreference to the accompanying drawings, in which;

[0019]FIG. 1 represents schematically the components required toimplement a transmission system using a coding device;

[0020]FIG. 2 is a schematic representation of a bit stream passingthrough the coding device; and

[0021]FIG. 3 represents schematically the components required toimplement a decoding device of the invention.

[0022]FIG. 1 shows an embodiment of a coding device for coding of adigital input in such a way as to increase the number of bits. This is astandard approach to provide forward error correction capability, andconvolutional coding is one common example. As shown in FIG. 1, achannel coding stage (for example convolutional coding) is followed byinter-frame interleaving, and with the interleaved output beingsubjected to rate matching, which may be puncturing or bit repetition.The puncturing or bit repetition is performed using adeletion/repetition pattern which targets a number of bits from thematrix of the interleaving circuit 16. The pattern is selected as afunction of the coding and interleaving operations, in such a way thatall bits of the digital input can be derived from non-targeted bits ofthe output of the interleaving circuit 16.

[0023]FIG. 1 shows a communication system 10 for the transmission on asingle channel of data from two data inputs 12, 22. Each data input isassociated with a respective coding device 13, 23 which performsconvolutional coding of the input, and also performs rate matching sothat the coded data can be modulated on to the available transmissionchannel which has a maximum channel capacity. Each coding device 13, 23comprises a respective channel coding circuit 14, 24. The channel codingcircuit in the example of FIG. 1 performs convolutional coding of thedata input. Standard convolutional coding circuitry is available, whichconverts a number k of input bits into a greater number n of outputbits, with the advantage that forward error correction may beimplemented. The coding rate is expressed as a ratio of the number ofinput bits to the number of output bits of the coding circuit, andstandard convolutional coding circuits are available with coding ratesof, for example, ½, ⅓, ¼, Convolutional coding circuits generallyinclude shift registers, function generators, a memory and amultiplexer. Each output bit of the convolutional coding circuitcomprises a known function executed on a given previous number of bitsof the input signal, depending upon the constraint length (the memorylength) of the coding circuit. There may be direct mapping of input bitsto the output as well as some functional transformations performed onthe input bits, to provide the additional error correction capability.Alternatively, there may be no direct mapping of input bits. The outputof the coding circuit can be decoded by corresponding decoding circuitryin order to regenerate the original data input as well as additionaldata suitable for error correction operations.

[0024] The convolutionally coded output word is supplied to aninterleaving circuit 16, 26 for combining a number of the convolutionaloutput words and producing a data block comprising a correspondingnumber of interleaved words. The simplest form of interleaving circuitcomprises a block interleaver which fills an interleaving matrix row byrow with a number of input words (corresponding to the interleavingdepth) and outputs the data column by column. Other interleaving schemesare also known. This process generally makes the transmission of dataless susceptible to errors caused by disruptions to the transmissionchannel.

[0025] The interleaved output is supplied to a rate matching circuit 18,28 which effectively changes the code rate of the convolutional codingcircuit, so that the output bit rate is more accurately controllable.This rate matching may comprise puncturing of the interleaved data block(namely removing bits) or may comprise bit repetition. It is known topuncture a convolutional coded output in order increase the code rate,and examples of this are given in U.S. Pat. No. 5,511,082.

[0026] An advantage of the structure of the coding device describedabove is that the rate matching operation follows the coding operation,with the result that the interleaving circuit 16, 26 has a constantinput bit rate governed by the bit rate of the data source and thereduction in the bit rate resulting from the convolutional codingcircuit 14, 24. Consequently, the need for adaptive interleavingcircuitry is avoided.

[0027] The rate matching pattern is selected, in accordance with theinvention, depending on the operation of the interleaving circuit andthe coding circuit.

[0028] This will be described in further detail with reference to FIG.2. The rate matching circuit 18, 28 also permits the channel coding forparticular data input to be adjusted to correspond to a particularquality of service requirement, for example concerning the errorperformance of the transmission channel. The rate matching circuits 18,28 in combination are also used to ensure that the overall bit rate ofthe signals, once multiplexed, does not exceed the transmission channelcapacity. Thus, a single rate matching operation can be used to achievespecific requirements of a transmission channel relating to anindividual data input, as well as ensuring that the combined datainformation can successfully be transmitted. There will be a trade offbetween the achievable error performance of the individual data channelsand the combined data rate, but these considerations are achieved with asingle rate matching circuit for each coding device.

[0029] The outputs of the two cod rig devices 13, 23 are multiplexedtogether by a multiplexing circuit 30 to enable transmission over thesingle channel. The output of the multiplexing circuit is effectively aframe of data for transmission over the channel, and the frame maycorrespond in size to one block of interleaved data. The frame data maybe interleaved by an intra-frame interleaving circuit 32 for subsequenttransmission by a conventional modulation and transmission circuit 34.

[0030] The operation of the coding device 13, 23 shown in FIG. 1 isshown in greater detail with reference to FIG. 2.

[0031]FIG. 2 part A shows, for the purposes of illustration, a sequenceof input data bits which are supplied to the coding device. These may bearranged as words of a predetermined number of bits or as a continuousdata stream as shown.

[0032] The channel coding circuit 14, 24 applies convolutional coding tothe input data stream and generates a bit stream having a greater numberof bits. In the example shown in FIG. 2, the convolutional codingcircuit converts a data stream of length k to a stream of length n, asshown, which effectively increases the number of bits for transmissionby n/k. Interleaving is applied to the coded data words and in theexample shown in FIG. 2 the inter-frame interleaving circuit 16 operateson 8-bit words from the coded data stream and applies a blockinterleaving algorithm with a depth of 4. Thus, the interleaving circuitbitwise fills an interleaving matrix of 4 columns and 8 rows, row byrow.

[0033] The block of data represented in FIG. 2 part C is subjected to adeletion or repetition pattern in order to alter the bit rate so thatall signals when multiplexed together produce a data stream which can behandled by the available transmission channel.

[0034] The applicant has recognised that the deletion or repetitionpattern should be selected such that the deleted or repeated bits shouldnot be required to enable all bits from the digital input to bereconstructed.

[0035] As one example, the assumption can be made that a convolutionalcoding circuit of low constraint length is employed. The effect of thisis that there is almost direct mapping between the coded data and theinput data, so that adjacent coded data bits will provide informationconcerning adjacent bits of the digital input signal. The deletion orrepetition of adjacent input bits should be avoided, because (i) in thecase of deletion of bits, the probability of error in transmission inrespect of that part of the input data is increased, and (ii) in thecase of repetition of bits, the extra capacity should be distributedevenly over the input data stream in order for the repetition to improvethe overall error performance of the transmission. It will be possibleto avoid deletion of adjacent bits in the digital input for lowpuncturing rates.

[0036] Simply applying deletion or repetition to the output of theinterleaving circuit 16, 26 may give poor results depending on theinterleaving depth (number of columns) and deletion/repetition rate. Forexample, if every fourth bit is deleted or repeated when the block ofdata represented by FIG. 2 part C is read out (column by column), theresult will be to delete or repeat four adjacent bits in the first row(A₁₁ to A₁₄) and in the fifth row (A₃₁ to A₃₄).

[0037] Consequently, in the deletion/repetition pattern shown in FIG. 2part D the bits for deletion or repetition have been selected with amaximum of one such bit on each row of the interleaving matrix. In theparticular example shown in FIG. 2, the deletion pattern for eachinterleaved word 44 is offset with respect to the adjacent interleavedword or words within the block. For example, interleaved word 44 a has adeletion/repetition pattern of (10000100) applied to it, whereasinterleaved word 44 b has a deletion/repetition pattern of (01000010)applied to it, and so on. By offsetting the pattern in adjacent columnsthe problem of deleting or repeating adjacent bits is avoided and thepattern is straightforward to implement.

[0038] In a more general case the details of the deletion/repetitionpattern chosen will depend on the size of the interleaving matrix andthe amount of deletion or repetition. In particular, the interleavingmatrix may be rather larger than the simple example shown in FIG. 2. Fora matrix having N columns a suitable deletion/repetition pattern may beobtained by selecting one bit in every P bits, proceeding row by rowthrough the matrix. If P is for example equal to N+1 a pattern similarto that in FIG. 2 part D, with adjacent columns offset by one row, willresult.

[0039] Also, the interleaving circuit 16, 26 may be more complex thanthat presented by way of example above. Many alternative interleavingcircuits suitable for use in a coding device in accordance with thepresent invention will be known to the skilled person, for examplere-ordering the columns of the interleaving matrix before it is readout. Hence the deletion/repetition pattern will need to be modified totake account of the characteristics of the interleaving circuit. Onemethod of doing this is to determine the maximum deletion/repetitionrate (say one bit in every P), and to apply an input data stream to theinterleaving circuit in which every Pth bit is set. The output from theinterleaving circuit is then a suitable deletion/repetition pattern. Itcan be seen that the deletion/repetition pattern of FIG. 2 part D couldhave been obtained by applying to the interleaving circuit 16, 26 a datastream in which every fifth bit was set.

[0040] The pattern shown in FIG. 2 part D may represent a maximum amountof puncturing or bit repetition which is allowed. In this case, forlower puncturing or repetition rates it would be possible to select onlya proportion of the deletion or repetition bits in order to achieve thedesired final bit rate.

[0041] A puncturing limit may be set as a general limit, or may bedetermined for each data input channel, even dynamically. In this case,deterministic algorithms or mappings for the exact puncturing can bedevised to achieve any particular puncturing rate. Non-uniformpuncturing grids may also be considered.

[0042] A puncturing or repetition pattern may be determined for themaximum interleaving depth, and the pattern for a different codingdevice within the communications system and having a differentinterleaving depth may be defined as a reduced number of columns of thelarger pattern. Each frame for transmission may then be associated withone of the possible puncturing columns (e.g. 44 a, 44 b), depending onthe interleaving depth, and the particular puncturing or repetition foreach frame can be determined by the receiving circuitry simply fromknowledge of the interleaving depth of the respective coding circuit,without additional signalling.

[0043] Although two input channels have been shown in the diagrams asbeing multiplexed together to be transmitted over a single channel, itis of course possible to multiplex together a much greater number ofinput channels.

[0044] Convolutional coding has been described as one particular exampleof coding technique, but other FEC schemes will be apparent to thoseskilled in the art, such as block coding schemes or turbo coding.

[0045] One particular application of the invention is for the up-linksignal from a mobile telecommunications station to a base station, andin which the mobile station can support different types of data source.A straightforward block interleaver has been described, although variousother interleaving options will be apparent to those skilled in the art.Whatever the interleaving method chosen, the repetition or deletionpattern implemented by the invention takes into account the effect ofthe interleaving operation so that the deletion/repetition pattern isselected having regard to the original data sequence.

[0046] A decoding device will also be required as part of a receivingsystem to form a complete communication system. An example of thedecoding device is shown schematically in FIG. 3, and comprises a datareconstruction circuit 50 which receives a de-multiplexed input. Thereconstructed data is supplied to a de-interleaving circuit 52, and to achannel decoder 54.

[0047] For a punctured transmission, the data reconstruction circuit 50fills in the punctured bits with dummy bits. This enables thede-interleaving to be performed to reconstruct the coded input sequence,but with some dummy bits. The decoding circuit can derive the locationof the dummy bits from the known interleaving matrix and the knownpuncturing pattern, and can thereby ignore the dummy bits during thereconstruction of the original data sequence.

[0048] For a transmission having repeated bits, the data reconstructioncircuit 50 will remove the bit repetitions, but will also use thoserepetitions to provide an estimation of the value of the respective bitwith lower probability of error. A soft combining technique may be usedto derive the most probable value for the bit concerned from theplurality of repetitions received.

[0049] The coding system described may be used only for an up-linktransmission in a cellular cordless telephone network, or it may be usedfor both the up- and down-link transmission channels in such a network.The system may be implemented in the UMTS cordless communicationsnetwork.

[0050] The present invention is applicable to radio communicationsystems such as UMTS.

1. A rate matching circuit for adjusting the number of bits in a datablock, the data block comprising a plurality of interleaved wordsgenerated by the action of an interleaving circuit on a coded outputgenerated by the action of a coding circuit on a digital input, thecoded output having a greater number of bits than the digital input, therate matching circuit having means for adjusting the number of bits inthe data block using a rate matching pattern to provide data bits fortransmission during respective frames of a transmission channel,characterised in that means are provided for selecting the rate matchingpattern depending on the characteristics of the coding circuit and ofthe interleaving circuit.
 2. A rate matching circuit as claimed in claim1, characterised in that the rate matching pattern is selected in such away that all bits of the digital input can be derived from the remainderof the bits in successive interleaved blocks.
 3. A rate matching circuitas claimed in claim 1 or 2, characterised in that the rate matchingpattern for each interleaved word within the data block is offset withrespect to the adjacent interleaved word or words within the block.
 4. Arate matching circuit as claimed in any one of claims 1 to 3,characterised in that the rate matching pattern is selected as afunction of the interleaving depth of the interleaving circuit.
 5. Acoding device comprising a rate matching circuit as claimed in any oneof claims 1 to 4, further comprising an interleaving circuit and acoding circuit.
 6. A decoding device comprising for decoding a signalcoded by a coding device as claimed in claim 5, and comprising a datareconstruction circuit for reconstructing the interleaved words, ade-interleaving circuit and a channel decoder.
 7. A communication systemcomprising a transmitter having a coding device as claimed in claim 5,and a receiver having a decoding device as claimed in claim
 6. 8. Asystem as claimed in claim 7, comprising a plurality of coding devices,each for coding a respective digital input, and a multiplexer forcombining output data words of the coding devices for subsequenttransmission by the transmission system on a single transmissionchannel.
 9. A system as claimed in claim 8, wherein the outputs ofdifferent coding devices are selected to have different data rates, thecombined data rate corresponding to the channel capacity of thetransmission channel.
 10. A method of operating a rate matching circuitto adjust the number of bits in a data block, the data block comprisinga plurality of interleaved words generated by the action of aninterleaving circuit on a coded output generated by the action of acoding circuit on a digital input, the coded output having a greaternumber of bits than the digital input, the rate matching circuitadjusting the number of bits in the data block using a rate matchingpattern to provide data bits for transmission during respective framesof a transmission channel, characterised by selecting the rate matchingpattern depending on the characteristics of the coding circuit and ofthe interleaving circuit.